Critical path monitoring techniques Adaptive voltage scaling

critical path monitoring technique adaptive voltage scaling

the voltage-frequency relationship chip can determined using approach in critical path monitor tries model critical path of chip.the critical path of system can duplicated using ring oscillator or fanout of 4 ring oscillator or delay line. critical path replica (delay line )provides closest behavior actual critical path except intra-die variations , cross coupling capacitances hard duplicate. delay line adapts environmental , process variations. actual performance of core , speed of delay line directly related, closed-loop adaptive voltage scaling system obtained automatically adjust supply voltage such minimum needed voltage supplied perform target task. delay chain consists of inverters, nand gates, wire segments,etc., , output can tapped 1 of points, allowing tuning of delay match chips critical path. reconfigurable delay chain can used in critical path monitoring technique. during manufacturing test, exact setting of delay chain determined. during avs operation, in order measure delay launch edge @ start of clock cycle , capture edge @ end of clock cycle @ output of delay chain , set of buffers. buffer outputs captured analyzed determine exact positioning of rising edge. feedback employed avs system continually adjusts supply voltage such delay chain , critical path meet timing constraints adequate margins. adjustment of supply voltage done such launched rising edge makes specified buffer stage ensures timing of delay line.

challenges in critical path monitoring techniques

sufficient safety margins included in order account mismatch between delay line(critical path monitor) , actual critical path in order account large within-die process variations inevitable.these large variations can cause critical path change 1 process corner other.thus in order maintain fail safe operation, additional delay margin maintained.this margin translated voltage overhead directly reduces energy savings associated avs approach.

the process , temperature variations of closed loop systems compensated continuously monitoring activity of critical path replica.nevertheless, in sub-micrometer technologies use of single reference in critical path becoming less feasible.as transistor dimensions scaled, selection of unique critical path across conditions becomes challenging.this because of increased variations of transistor , wires progress of technology node.also when contribution of interconnect delay increases, there might several paths have different combinations of logic , interconnect delay overall delays being close each other.in case selection of critical path becomes more challenging.