Implementation of circuit that monitors On-chip-variations in the AVS systems Adaptive voltage scaling

1 implementation of circuit monitors on-chip-variations in avs systems

1.1 critical path monitoring techniques

1.1.1 challenges in critical path monitoring techniques


1.2 razor approach

1.2.1 challenges in razor approach

implementation of circuit monitors on-chip-variations in avs systems

the closed loop voltage scaling system utilizes on chip circuit structures provide feedback required adaptively track actual silicon behavior. 1 commonly used approach use ring oscillator operates @ same voltage of rest of chip. voltage-frequency relationship chip @ particular frequency determined frequency of ring oscillator.

critical path monitoring techniques

critical path monitoring technique adaptive voltage scaling

the voltage-frequency relationship chip can determined using approach in critical path monitor tries model critical path of chip.the critical path of system can duplicated using ring oscillator or fanout of 4 ring oscillator or delay line. critical path replica (delay line )provides closest behavior actual critical path except intra-die variations , cross coupling capacitances hard duplicate. delay line adapts environmental , process variations. actual performance of core , speed of delay line directly related, closed-loop adaptive voltage scaling system obtained automatically adjust supply voltage such minimum needed voltage supplied perform target task. delay chain consists of inverters, nand gates, wire segments,etc., , output can tapped 1 of points, allowing tuning of delay match chips critical path. reconfigurable delay chain can used in critical path monitoring technique. during manufacturing test, exact setting of delay chain determined. during avs operation, in order measure delay launch edge @ start of clock cycle , capture edge @ end of clock cycle @ output of delay chain , set of buffers. buffer outputs captured analyzed determine exact positioning of rising edge. feedback employed avs system continually adjusts supply voltage such delay chain , critical path meet timing constraints adequate margins. adjustment of supply voltage done such launched rising edge makes specified buffer stage ensures timing of delay line.

challenges in critical path monitoring techniques

sufficient safety margins included in order account mismatch between delay line(critical path monitor) , actual critical path in order account large within-die process variations inevitable.these large variations can cause critical path change 1 process corner other.thus in order maintain fail safe operation, additional delay margin maintained.this margin translated voltage overhead directly reduces energy savings associated avs approach. process , temperature variations of closed loop systems compensated continuously monitoring activity of critical path replica.nevertheless, in sub-micrometer technologies use of single reference in critical path becoming less feasible.as transistor dimensions scaled, selection of unique critical path across conditions becomes challenging.this because of increased variations of transistor , wires progress of technology node.also when contribution of interconnect delay increases, there might several paths have different combinations of logic , interconnect delay overall delays being close each other.in case selection of critical path becomes more challenging.

razor approach

in order overcome bottlenecks of critical path approach implementation of avs system, razor approach used. unlike critical path approach single path identified critical path, razor approach has set of potential critical paths monitored. in approach on-chip timing checker employed check timing margin of set of critical path. delayed version of system clock used timing circuit capture data in shadow latch same data captured master(main) flipflop. wherever sub paths become critical, additional shadow latches introduced. when supply voltage scaled value latched in main flipflop might different of latched shadow latches, results in error signals. error signals shadow latches gathered generate single error indicator. error corrected flushing pipeline , reloading state existing before error occurred. when error rates decrease beyond limits supply voltage reduced till point error tends become unacceptable.

challenges in razor approach

in order guarantee robust operation system characterization @ conditions known requires increased number of latches. increases error probability overhead of error detection circuit.
when error rate increases, latency arises due flushing of pipeline might negatively affects overall system performance.
when design has many critical paths close each other in timing, more shadow latches needed resulting in increased overhead , reduced efficiency. increases complexity of razor approach.




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